Technical Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to a three-dimensional (3D) resist profile aware etch-bias model.
Related Art
Rapid advances in computing technology have made it possible to perform trillions of computational operations each second on data sets that are sometimes as large as trillions of bytes. These advances can be attributed to the dramatic improvements in semiconductor manufacturing technologies, which have made it possible to integrate tens of millions of devices onto a single chip.
As semiconductor design enters the deep submicron era, process model accuracy and efficiency is becoming increasingly important. Inaccuracies in the process model negatively affect the efficacy of downstream applications. For example, inaccuracies in the etch-bias model can cause lithography verification to be inaccurate. If the process model is computationally inefficient, it can increase the time-to-market for an integrated circuit, which can cost millions of dollars in lost revenue. Hence, it is desirable to improve the accuracy and the efficiency of a process model.